CDR circuits (or systems) are generally used to sample an incoming data signal, extract (or recover) the clock from the incoming data signal, and retime the sampled data to produce one or more recovered data bit streams. A phase-locked loop (PLL)-based CDR circuit is a conventional type of CDR circuit. A PLL circuit is an electronic control system that may be used, in part or in whole, to generate or maintain one signal that is locked onto the phase and frequency of another signal. By way of example, in a conventional PLL-based CDR, a phase detector compares the phase between input data bits from a serial input data stream and a clock signal generated by a voltage-controlled oscillator (VCO). In response to the phase difference between the input data and the clock, the phase detector generates phase or frequency correction signals. A charge pump drives a current to or from a loop filter according to the correction signals. The loop filter outputs a control voltage VCTRL for the VCO based on the current driven by the charge pump. The loop acts as a feedback control system that tracks the phase and frequency of the input data stream with the phase and frequency of the clock that the loop generates.
One significant problem with conventional CDR systems comprising two CDR circuits that each receive a respective input data bit stream is that such CDR systems are suitable only for full-rate CDR within each individual CDR circuit without data demultiplexing; that is, when the frequencies of the recovered clock signals generated for each input data bit stream and the data rates (or frequencies) of the recovered data bit streams generated for each input data bit stream share the same frequency or rate as the respective input data bit streams. Otherwise, there exists an uncertainty in the relative clock and data phases from each CDR circuit and the system may operate erroneously. Unfortunately, many, or even most, practical CDR systems in, for example, high speed optical communication applications, use either half-rate or quarter-rate CDR architectures, or demultiplex each of the input data bit streams to two, four, or more individual streams to, for example, cope with high input data rates.